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mt9p111: 1/4-inch 5 mp soc digital image sensor features ? mt9p111_ds rev. g pub. 5/15 en 1 ?semiconductor components industries, llc 2015, 1/4-inch 5 mp system-on-a-chip (soc) cmos digital image sensor mt9p111 datasheet, rev. g for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance ? ultra-low-power, low-cost ? anti-shake support ? one time programmable memory (otpm) for automatic positional gain adjustments and other uses ? parallel data output and serial mobile industry processor interface (mipi) data output ? integrated real-time jpeg encoder ? flexible support for external auto focus ? internal master clock generated by on-chip phase-locked loop (pll) oscillator ? electronic rolling shutter (ers), progressive scan ? integrated image flow processor (ifp) for single-die camera module ? automatic image correction and enhancement ? selectable output data format: ycbcr, 565rgb, 555rgb, 444rgb, jpeg 4:2:2, processed bayer, raw8- and raw10-bit ? output fifo for data rate equalization ?programmable i/o slew rate ? xenon and led flash support with fast exposure adaptation ? configurable gamma correction based on scene brightness ? arbitrary image scalin g with anti-aliasing ? two-wire serial interface providing access to registers and microcontroller memory, additional serial interface under user control ? includes internal vcm driver and access to internal a/d converter applications ? cellular phones ?pc cameras ?pdas table 1: key performance parameters parameter value optical format 1/4-inch full resolution 2592 x 1944 pixels pixel size 1.4 ? m x 1.4 ? m dynamic range 62 db snr max 35.2 db responsivity 0.68 v/lux-sec chief ray angle 25.11 max at 80% image height color filter array rgb bayer pattern active pixel array area 3.62 mm x 2.72 mm shutter type electronic rolling shutter (ers) and global reset release (grr) input clock frequency 10 ? 48 mhz maximum frame rate 15 fps at full resolution (jpeg), 30 fps in preview mode (vga bin2 skip2) maximum pixel data output mipi: 768 mb/s max parallel: 96 mp/s maximum pixel clock frequency 96 mhz supply voltage analog 2.5 ? 3.1 v digital 1.7 ? 1.95 v i/o 1.7-1.9v or 2.5C3.1 v pll 2.5 ? 3.1 v mipi 2.5C3.1 v adc resolution 12-bit, on-die power consumption 550 mw at 30 fps, 1280 x 720 video mode 401 mw at 30 fps, hp preview mode 230 mw at 23 fps, preview lp mode current consumption 10 ? a, shutdown, at +70c operating temperature (at junction) C30c to +70c
mt9p111_ds rev. g pub. 5/15 en 2 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9P111D00STCK28AC1-200 5 mp 1/4" soc die sales, 200 ? m thickness
mt9p111_ds rev. g pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 mt9p111 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sensor core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 soc description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 jpeg encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 anti-shake (as) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 camera control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
mt9p111_ds rev. g pub. 5/15 en 4 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor list of figures list of figures figure 1: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 2: soc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 3: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 4: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: 6 pixels in normal and column mirror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: six rows in normal and row mirro r readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: 8 pixels in normal and column sk ip 2x readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: pixel readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: pixel readout (column skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: pixel readout (row skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: pixel readout (column and row sk ipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: pixel readout (column binning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: pixel readout (column and row bi nning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: valid image data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: color pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 18: color bar test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 19: gamma correction curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 20: timing of full frame data or scaled data passing th rough the fifo . . . . . . . . . . . . . . . . . . . . . . . . . .2 8 figure 21: jpeg continuous data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 22: jpeg spoof mode timing with co ntinuous clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 23: jpeg spoof mode timing with ad aptive clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 24: jpeg spoof mode timing with thumbnail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 25: jpeg status segment structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 26: anti-shake algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 27: firmware architecture block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 28: vcm driver typical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 29: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 30: single read from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 31: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 32: sequential read, start from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 33: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 34: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 35: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 36: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 37: hard reset signal sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 38: soft reset signal sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 39: hard standby signal sequence mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 40: soft standby signal sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 41: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 42: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 43: sequence of signals for otp memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 44: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
mt9p111_ds rev. g pub. 5/15 en 5 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4: row address sequencing (sampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 5: row address sequencing (binning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 6: data formats supported by mipi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7: ycbcr output data ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 8: rgb ordering in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 9: 2-byte rgb format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10: vgpio configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 11: trigger control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 12: vcm driver typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 13: power-up signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 14: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 15: hard reset signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 16: soft reset signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 17: hard standby signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 18: soft standby signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 19: dc electrical definitions and characteristics?parallel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 20: i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 21: i/o timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 22: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 23: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 24: supplies voltages and clock frequency for otp memory programming . . . . . . . . . . . . . . . . . . . . . . .63 table 25: status of signals during different states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
mt9p111_ds rev. g pub. 5/15 en 6 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor mt9p111 overview mt9p111 overview the mt9p111 has a color image sensor with a bayer color filter arrangement and a 5mp active-pixel array with electronic rolling shut ter (ers). the sensor co re readout is 12-bit, supports skipping and binning, and can be flipped and/or mirrored. the sensor core also supports separate analog and digi tal gain for all four color channels (r, gr, gb, b). the mt9p111 also has an embedded phase-lo cked loop oscillator (pll) that can generate the internal sensor clock from th e common clock signals available in typical mobile phone systems. when in use, the pl l adjusts the incoming clock frequency up, allowing the mt9p111 to run at almost any de sired resolution and frame rate within the sensor's capabilities. the pll can be bypassed and powered down to reduce power consumption. the mt9p111 has numerous power-conserving features including a soft standby mode and a hard standby mode. in standby mode, the sensor can be configured to consume less power than normal operation, with the option of retaining a limited amount of the internal configuration settings. by default, entering standby disables the internal v dd power rail. in addition, there is a shutdown mode that will disable the power supplies in order to achieve the lowest power consumption possible. the mt9p111 can be used with either a serial mipi interface or the parallel data output interface, which has a programmable i/o slew rate to minimize emi and an output fifo to eliminate output data bursts. jpeg format can be output in both the mipi and the parallel data output interfaces. exif, mipi data type support is also included, along with scalado support. the advanced image flow processor (ifp) an d flexible programmability of the mt9p111 provide a variety of ways to enhance and op timize the image sensor performance. built- in optimization algorithms enable the mt9p111 to operate at factory settings as a fully automatic, highly adaptable camera; howeve r, most of its settings are user-program- mable. these algorithms include black level conditioning, shading correction, defect correc- tion, noise reduction, color interpolation, color correction, aperture correction, and image formatting such as cropping and scaling. the mt9p111 also includes a sequencer that c oordinates all events triggered by the user. the sequencer manages auto focus, auto white balance, flicker detection, anti-shake, and auto exposure for the different operating modes, which include preview, still capture, video, and snapshot with flash. all modes of operation are individually conf igurable and are organized as two contexts. a context is defined by sensor image size, frame rate, resolution, and other associated parameters. the user can switch between the two contexts by sending a command through the two-wire serial interface. a two-wire serial register interface bus enab les read/write access to control registers, variables, and special function registers within the mt9p111. the hardware registers include sensor core controls, color pipeline controls, and output controls. the general purpose vgpio can be configured to allow the user extended platform func- tionality or achieve a 10-bit parallel bayer output.
mt9p111_ds rev. g pub. 5/15 en 7 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor signal description signal description table 3 provides the signal descriptions for the mt9p111. table 3: signal descriptions name type description notes standby input controls sensors standby mode, active high. reset_bar input master reset signal, active low (can be left floating if not used). shutdown input complete shutdown function for lowest power state (must be tied to d gnd if not used) extclk input input clock signal 10C48 mhz. fo r low leakage, do not ov erdrive input signal. v pp input high voltage programming pin for one-time programmable (otp) memory (must be left floating for normal operation). sclk input slave two-wire serial interface clock from the host processor. s addr input selects device address for the slave two-wire serial interface. the address is 0x78 when s addr is tied low, 0x7a if tied high. s data i/o slave two-wire serial interface data to and from the host processor. s_scl output master two-wire serial interface cl ock to peripheral devices like af mechanics. s_sda i/o master two-wire serial interface data to peripheral devices like af mechanics. vgpio[7:0] i/o general purpose digital i/o, used for auto focus function (can be left floating if not used). d out [7:0] output 8-bit image data output or most significant bits (msb) of 10-bit soc bypass mode. if 10- bit bayer is desired, vgio[1:0] can be configur ed to output two least significant bits (lsb). pixclk output pixel clock. used for sampling d out , frame_valid, and line_valid. line_valid output identifies pixels in the active line. frame_valid output identifies rows in the active image. dout_n output differential mipi data (sub-lvds, negative) (must be left floating if not used). dout_p output differential mipi data (sub-lvds, positive) (must be left floating if not used). clk_n output differential mipi clock (sub-lvds, ne gative) (must be left floating if not used). clk_p output differential mipi clock (sub-lvds, po sitive) (must be left floating if not used). vcm_out i/o vcm actuator driver pad. vcm_gnd i/o ground pad for vcm_out. atest0 i/o internal adc access (leave floating if not used). atest1 i/o internal adc access (leave floating if not used). test_en input test enable (must be tied to d gnd ). v dd supply digital power (1.8v typical). vaa_pix supply pixel array power (2.8v typical). v aa supply analog power (2.8v typical). v dd _pll supply pll power (2.8v typical). v dd _io supply i/o power supply (1.8v or 2.8v typical). gnd_io supply i/o ground. d gnd supply digital ground. 1 a gnd supply analog ground. 1 v dd io_tx supply i/o power supply for the mipi output interf ace, 2.8v typical, can be disconnected if the interface is not used. gndio_tx supply i/o ground supply for the mipi output interf ace. can be disconnected if the interface is not used).
mt9p111_ds rev. g pub. 5/15 en 8 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor typical connections note: a gnd and d gnd are not connected internally (inside the chip). typical connections figure 1 on page 9 shows typical mt9p111 devi ce connections. for low-noise operation, the mt9p111 requires separate power supplies for analog and digital. incoming digital and analog ground conductors can be tied to gether next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. on semiconductor does not recommend the use of inductance filters on the power supplies or output signals. the mt9p111 supports different digital core (v dd /d gnd ), mipi output (v dd io_tx/ gndio_tx), and i/o (v dd _io/gnd_io) power domains that can be at different volt- ages. the pll requires a clean power source (v dd _pll). v dd _vgpio supply i/o power supply for vgpio[7:0] signals. ca n be either 1.8 v or 2.8 v typical. must be connected even if not used. gnd_vgpio supply i/o ground for vgpio[7:0]. must be connected even if not used. table 3: signal descriptions name type description notes
mt9p111_ds rev. g pub. 5/15 en 9 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor typical connections figure 1: typical configuration (connection) notes: 1. this typical configuration shows only one scenar io out of multiple possibl e variations for this sen- sor. the minimum recommended decoupling configuration is 0.1 ? f per supply on module and 10 ? f off module. 2. if a mipi interface is not required, the following pads must be left floating: d out _p, d out _n, clk_p, and clk_n. 3. the vgpio pads can serve multiple features that can be reconfigured. the function and direction will vary by applications. if vg pio pads are not required, the v dd _vgpio, gnd_vgpio, and vgpio[7:0] pads can be left floating. 4. only one of the output modes (serial or parallel) can be used at any time. 5. on semiconductor recommends a resistor value of 1.5k ? to v dd _io for the two-wire serial inter- face rpull-up; however, greater values ma y be used for slower transmission speeds. 6. v aa and vaa_pix must be tied together. 7. v pp is the one-time programmable (otp) memory pr ogramming voltage and should be left floating during normal operation. 8. v dd io_tx can be connected to v dd _io if v dd _io = 2.8v. if the mipi output is not used, v dd io_tx can be tied to the v aa supply if an on semiconductor-reco mmended decoupling capacitor is used. v dd io_tx must be connected to a 2.8v supply. v aa /vaa_pix analog power s data sclk standby 9 gnd_io a gnd i/o power digital core power v dd pll power v dd _pll v aa 6 vaa_pix 6 slave two-wire serial interface r pull - up 5 reset_bar s addr test_en standby mode extclk external clock in (10C48 mhz) active low reset d gnd v dd to serial camera port v dd _io v dd io_tx 8 v dd _io v dd _vgpio 3 gnd_vgpio 3 vgpio[7:0] 3 general purpose inputs gndio_tx shutdown 9 low-power shutdown mode s_scl s_s data mipi tx power v pp 7 vcm_out gndio_vcm frame_valid pixclk line_valid clk_p d out _p clk_n d out _n to vcm actuator to parallel camera port or 4 d out [7:0] atest0 atest1 multi-master two-wire serial interface
mt9p111_ds rev. g pub. 5/15 en 10 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor architecture overview 9. if standby and shutdown pins are not used, they must be connected to d gnd . decoupling capacitor recommendations the minimum decoupling capacitor recommendation is 0.1 ? f per supply in the module. it is important to provide clean, well re gulated power to each power supply. the on semiconductor recommendation for capacitor placement and values are based on our internal demo camera design and verified in hardware. note: since hardware design is influenced by many factors, such as layout, operating condi- tions, and component selection, the customer is ultimately responsible to ensure that clean power is provided for their own designs. in order of preference, on semiconductor recommends: 1. mount 0.1f and 1f decoupling capacitors for each power supply as close as possi- ble to the pad and place a 10 f capacitor nearby off-module. 2. if module limitations allow for only six decoupling capacitors for a three-regulator design (v dd _pll tied to v aa ), use a 0.1f and 1f capacitor for each of the three reg- ulated supplies. on semiconductor also recommends placing a 10f capacitor for each supply off-module, but close to each supply. 3. if module limitations allow for only three decoupling capacitors, a 1f capacitor for each of the three regulated supplies is preferred. on semiconductor recommends placing a 10f capacitor for each supply off-module but closed to each supply. 4. if module limitations allow for only three decoupling capacitors, a 0.1f capacitor for each of the three regulated supplies is preferred. on semiconductor recommends placing a 10f capacitor for each supply off-module but close to each supply. 5. priority should be given to the v aa supply for additional decoupling capacitors. 6. inductive filtering components are not recommended. 7. follow best practices when performing physical layout. refer to technical notes tn-09-131 and tn-09-214. architecture overview the mt9p111 combines a 5mp sensor core with an image flow processor (ifp) to form a stand-alone solution that includes both image acquisition and processing. both the sensor core and the ifp have internal regist ers that can be controlled by the user. in normal operation though, an integrated mi crocontroller autonomo usly controls most aspects of operation. the processed image data is transmitted to the host system either through a parallel bus or a serial data interface through the output interface.
mt9p111_ds rev. g pub. 5/15 en 11 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor architecture overview figure 2: soc block diagram color pipeline mipi transmitter internal register bus stats engine microcontroller internal sensor core image flow processor output interface fifo sram rom jpeg pll
mt9p111_ds rev. g pub. 5/15 en 12 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description sensor core description the sensor core of the mt9p111 is a progress ive-scan sensor that generates a stream of pixel data at a constant frame rate, qualified by line_valid (lv) and frame_valid (fv). the maximum pixel rate is 96 mp/s, corresponding to a pixel clock rate of 96 mhz. figure 3 shows a block diagram of the sensor co re. it includes a 5mp active-pixel array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate inci dent light. the exposure is controlled by varying the time interval between reset and re adout. once a row has been read, the data from the columns is sequenced through an anal og signal chain (providing offset correc- tion and gain), and then through an adc. the output from the adc is a 12-bit value compressed to a 10-bit value for each pixel in the array. the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for the offset-correction algorithms (black level control). the sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers are controlled by th e soc firmware and can be accessed through a two-wire serial interface. register values written to the sensor core maybe overwritten by firmware. the output from the core is a bayer pattern; alternate rows are a sequence of either green and red pixels or blue and green pixels. the o ffset and gain stages of the analog signal chain provide per-color control of the pixel data. a flash strobe output signal is provided to al low an external xenon or led light source to synchronize with the sensor exposure time. additional i/o signals support the provision of an external mechanical shutter. figure 3: sensor core block diagram sensor core active-pixel sensor (aps) array timing and control control registers gr /gb channel red /blue channel pll 10-bit data out r / ggb r/b r / ggb r/b analog processing adc digital processing
mt9p111_ds rev. g pub. 5/15 en 13 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description pixel array the sensor core uses a bayer color pattern, as shown in figure 4. figure 4: pixel color pattern detail (top right corner) default readout order when the sensor is operating in a system, the active surface of the sensor faces the scene as shown in figure 5. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced. by convention, data from the sensor is shown with the first pixel read out in the case of the sensor core in the top left corner. figure 5: imaging a scene b gr b gr b g2 r gb r gb b gr b gr b g2 r gb r gb b gr b gr b g2 r g2 r g2 black pixels column readout direction . . . ... row readout direction first clear pixel lens pixel (0,0) row readout order column readout order scene sensor (rear view)
mt9p111_ds rev. g pub. 5/15 en 14 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description pll pll-generated clocks the pll can generate a pixel clock signal whose frequency is up to 96 mhz, using a extclk input of 10 through 48 mhz. pll setup because the input clock frequency is unknow n, the sensor starts up with the pll disabled. the pll takes time to power up. the behavior of its output clock signal during lock phase is not guaranteed. another limitati on is that the pll_bypass cannot be turned off until after the analog core is powered up . failure to do so may make the clocking inoperable. digital processing readout options the sensor core supports different readout opti ons to modify the image before it is sent to the ifp. the readout can be limited to a sp ecific window of the original pixel array. for preview modes, the sensor core supports both skipping and binning in x and y direc- tions. by changing the readout direction the imag e can be flipped in the vertical and/or mirrored in the horizontal. window size the image output size is set using firmware variables. the edge pixels in the array are present to avoid edge defects and should not be included in the visible window. binning or skipping will change the image output size.
mt9p111_ds rev. g pub. 5/15 en 15 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description readout modes horizontal mirror when the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed. figure 6 shows a sequence of 6 pixels being read out with normal readout and reverse readout. figure 6: 6 pixels in normal and column mirror readout modes vertical flip when the sensor is configured to flip the image vertically, the order in which pixel rows are read out is reversed. figure 7 shows a sequ ence of 6 rows being read out with normal readout and reverse readout. figure 7: six rows in normal and row mirror readout modes column and row skip the sensor core supports subsampling. su bsampling reduces the amount of data processed by the analog signal chain in the sensor and thereby allows the frame rate to be increased. this reduces the amount of ro w and column data processed and is equiva- lent to the skip2 readout mode provided by earlier on semiconductor imaging sensors. when enabling subsampling, the proper imag e output and crop sizes must be updated beforehand. d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) reverse readout g2 (9:0) r2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) d out [9:0] frame_valid n ormal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out [9:0] r everse readout row4 (9:0) row5 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) row0 (9:0)
mt9p111_ds rev. g pub. 5/15 en 16 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description figure 8: 8 pixels in normal and column skip 2x readout modes pixel readouts the following diagrams show a sequence of data being read out with no skipping. the effect of the different subsampling on the pixel array readout is shown in figures 9 through 13. figure 9: pixel readout (no skipping) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) d out [9:0] line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) r2 (9:0) x incrementing y incrementing
mt9p111_ds rev. g pub. 5/15 en 17 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description figure 10: pixel readout (column skipping) figure 11: pixel readout (row skipping) x incrementing y incrementing x incrementing y incrementing
mt9p111_ds rev. g pub. 5/15 en 18 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description figure 12: pixel readout (column and row skipping) table 4: row address sequencing (sampling) normal subsampled sequence 1 subsampled sequence 2 00 no data 11 no data 2no data 2 3no data 3 44 no data 55 no data 6no data 6 7no data 7 x incrementing y incrementing
mt9p111_ds rev. g pub. 5/15 en 19 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description binning the mt9p111 sensor core supports 2 x 1, 2 x 2, and bin2-skip4 analog binning (column binning, also called x-binning and row/column binning , also called xy-binning). binning has many of the same characteristics as subsampling but because it gathers image data from all pixels in the active window (rather than a subset of them), it achieves superior image quality and avoids the aliasing artifacts that can be a characteristic side effect of subsampling. binning is enabled by selecting the approp riate subsampling setti ngs. subsampling may require sensor window size adjust ment when binning is enabled. the effect of the different subsampling sett ings is shown in figure 13 and figure 14 on page 19. figure 13: pixel readout (column binning) figure 14: pixel readout (column and row binning) y incrementing x incrementing y incrementing x incrementing
mt9p111_ds rev. g pub. 5/15 en 20 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description binning limitations the sensor must be taken out of streamin g mode before switching between binned and non-binned operation. binning requires diffe rent sequencing of the pixel array and imposes different timing limits on the operation of the sensor. in particular, xy-binning requires two read operations from the pixel ar ray for each line of output data, which has the effect of increasing the minimum line blanking time. raw data format the sensor core image data is read out in a progressive scan. valid image data is surrounded by horizontal blanking and vert ical blanking, as shown in figure 15 on page 20. the amount of horizont al blanking and vertical bl anking is programmable. lv is high during the shaded region of the figure. figure 15: valid image data raw data timing d out [9:0]is synchronized with th e pixclk output. when lv is high, one pixel?s data is output on the 10-bit d out output bus every pixclk period. by default, the pixclk signal runs at the same frequency as the mast er clock, and its rising edges occur one-half table 5: row address sequencing (binning) normal binning sequence 1 binning sequence 2 00,2 no data 11,3 no data 2no data 2,4 3no data 3,5 44,6 no data 55,7 no data 6no data 6,8 7no data 7,9 p 0,0 p 0,1 p 0,2 ................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 ................................p 1,n-1 p 1,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 p m-1,0 p m-1,1 .........................p m-1,n-1 p m-1,n p m,0 p m,1 .........................p m,n-1 p m,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ................................ 00 00 00 00 00 00 ................................ 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
mt9p111_ds rev. g pub. 5/15 en 21 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor sensor core description of a master clock period after transitions on lv, fv, and d out (see figure 16). this allows pixclk to be used as a clock to sample th e data. pixclk is continuously enabled by default (but is config urable), even during the blanking period. figure 16: pixel data timing example power reduction modes low power mode the mt9p111 supports low power operation during preview mode by reducing the pixel clock frequency. when the mt9p111 enters preview mode with low power mode enabled (sensor core register 0x3040[9] = 1), the sens or clock will be reduced by half. internal logic will disable the pixel clock and re-program the divider value. internal delay will be applied during this change to avoid any clock glitches. dynamic power mode dynamic power mode setting can also be used to significantly reduce the power levels in the sensor. dynamic power mode will turn off power to the analog portions of the sensor that are not being utilized. the following registers need to be asserted to enter dynamic power modes: reg = 0x3170[11] = 1, enable dynamic power modes reg = 0x3eda[6] = 1 reg = 0x3eda[14] = 1 reg = 0x3eda[15] = 1 p 0 (9:0) p 1 (9:0) p 2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking line_valid pixclk d out [9:0]
mt9p111_ds rev. g pub. 5/15 en 22 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description soc description image flow processor image and color processing in the mt9p 111 are implemented as an image flow processor (ifp) coded in hardware logic. during normal operation, the embedded microcontrolle r will automatically adjust the oper ation parameters. the ifp is broken down into different sections, as outlined in figure 17. figure 17: color pipeline test pattern generator black level subtraction color correction aperture correction gamma correction (12-to-8 lookup) statistics engine color kill scaler output formatting yuv to rgb tx fifo raw data 10/12-bit rgb raw 10 8-bit rgb 8-bit yuv parallel output mipi serial output output interface rgb to yuv digital gain control lens shading correction defect correction, noise reduction, color interpolation, sharpening mux mipi ifp parallel output jpeg pixel array adc
mt9p111_ds rev. g pub. 5/15 en 23 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description test patterns during normal operation of the mt9p111, a stream of raw image data from the sensor core is continuously fed into the color pipeline. for test purposes, this stream can be replaced with a fixed image generated by a special test module in the pipeline. the module provides a selection of test patterns sufficient for basic testing of the pipeline. test patterns are accessible by programming a register and are shown in figure 18. disabling the mcu is recommended before enabling test patterns. figure 18: color bar test pattern test pattern example flat field vertical ramp color bar vertical stripes pseudo-random
mt9p111_ds rev. g pub. 5/15 en 24 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description black level subtract ion and digital gain image stream processing starts with black level subtraction and multiplication of all pixel values by a programmable digital gain. both operations can be independently set to separate values for each color channel (r, gr, gb, b). independent color channel digital gain can be adjusted with registers. independent color channel black level adjust- ments can also be made. if the black level su btraction produces a negative result for a particular pixel, the value of this pixel is set to ?0.? automatic positional gain adjustments (apga) lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9p111 has an embedded shading correction module that can be programmed to counter the shading effects on each individual r, gb, gr, and b color signal. in some cases, different lighting condit ions can introduce different color shading response. to compensate for the dependency of the lens shading to the illuminant that can result, different settings of lens shading co rrection (lc) coefficients can be used. the mt9p111 provides up to three settings to be stored. each pga setting should be opti- mized at a particular color temperature. in the mt9p111, color temperature is detected, stored in the firmware variable ccmposition, and an appropriate pga setting is applied. the variable (ccmposition) has a range from 0 through 255 and reflects the current color temperature, 0 corresponding to lowest colo r temperature, 255 the highest. the host specifies a range of ccmposition values for a particular pga setting. the ranges should overlap to provide hysteresis and prevent thrashing between pga settings. the correction function for each illuminant, color-dependent solutions are calibrated using the sensor, lens system, and an image of an ev enly illuminated, featureless gray calibration field. from the resulting image, the color correction functions can be derived. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 1) where p are the pixel values and f is the color dependent correction functions for each color channel. p corrected (row,col)=p sensor (row,col)*f(row,col)
mt9p111_ds rev. g pub. 5/15 en 25 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description one-time programmable memory the mt9p111 contains 5kb of otp memory, suitable for storing three separate lens shading correction settings, color calibration, external mechanisms, initialization settings, and module identification that ca n be programmed during the module manu- facturing process. programming the otp memory requires the use of a high voltage at the v pp pin. during normal operation, the v pp pin should be left floating. the otp memory can be accessed through the two-wire serial interface. refer to the mt9p111 developer guide for programming procedures. there is a one-time programmable memory timing calculator available for customer use. please contact on semiconductor engineering support. defect correction and noise reduction the ifp performs continuous de fect correction that can mask pixel array defects such as high dark-current (hot) pixels and pixels that are darker or brighter than their neighbors due to photoresponse nonuniformity. the modu le is edge-aware with exposure that is based on configurable thresholds. the thre sholds are changed continuously based on the brightness of the current scene. noise reduction can be enabled and disabled and thresholds can be set through register settings. color interpolation in the raw data stream fed by the sensor core to the ifp, each pixel is represented by a 10-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue , depending on the pixel's position under the color filter array. initial data processing step s, up to and including the defect correction, preserve the one-color-per-pixel nature of th e data stream, but after the defect correc- tion it must be converted to a three-colors -per-pixel stream appropriate for standard color processing. the conversion is done by an edge-sensitive color interpolation module. the module pads the incomplete color information available for each pixel with information extracted from an appropri ate set of neighboring pixels. the algorithm used to select this set and extract the in formation seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. the edge threshold can be set th rough register settings. color correction and aperture correction to achieve good color fidelity of the ifp outp ut, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the three components of the resulting color vector are all sums of three 10-bit numbers. since such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12-bits per color (36 bits per pixel). the color correction matrix can be either programmed by the user or automatically selected by the auto white balance (awb) algorithm implemented in the ifp. color correction should ideally produce output colors that ar e corrected for the spectral sensitivity and color crosstalk characteristics of the imag e sensor. the optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. the color co rrection variables can be adjusted through register settings. to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through register settings.
mt9p111_ds rev. g pub. 5/15 en 26 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description image cropping by configuring the cropped and output wind ows to various sizes, different zooming levels for example 4x, 2x, and 1x can be achi eved. the location of the cropped window is also configurable so that panning is also supported. a separate cropped window is defined for context a and context b. in both contexts, the height and width definitions for the output window must be equal to or smaller than the cropped image. gamma correction the gamma correction curve (as shown in figure 19 on page 26) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. the absc issas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. the 8-bit ordinates are programmable through ifp registers. the mt9p111 ifp includes a block for gamma co rrection that can adjust its shape based on brightness to enhance the performance under certain lighting conditions (see figure 19 on page 26). three custom gamma correction tables may be uploaded corre- sponding to a brighter lighting condition, a normal lighting condition, and a darker lighting condition. at power-up, the ifp load s the three tables with default values. the final gamma correction table used depends on the brightness of the scene and can take the form of either uploaded tables or an inte rpolated version of two of the three tables. a single (non-adjusting) table for al l conditions can also be used. figure 19: gamma correction curve special effects special effects like negative image, sepia, or b/w can be applied to the data stream at this point. these effects can be enabled and selected by registers. rgb to yuv conversion for further processing, the data is converted from rgb color space to yuv color space. gamma correction input rgb, 12-bit output rgb, 8-bit 0 300 250 200 150 100 50 0 1,000 2,000 3,000 4,000 0.45
mt9p111_ds rev. g pub. 5/15 en 27 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description color kill to remove high or low light color artifacts, a color kill circuit is included. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proporti onally to the difference between their lumi- nance and the threshold. yuv color filter as an optional processing st ep, noise suppression by one-dimensional low-pass filtering of y and/or uv signals is possible. a 3- or 5-tap filter can be selected for each signal. image scaling to ensure that the size of images output by the mt9p111 can be tailored to the needs of all users, the ifp includes a scaler module. when enabled, this module performs resca- ling of incoming images?shrin ks them to arbitrarily selected width and height without reducing the field of view and without discarding any pixel values. the scaler performs pixel binning?divides each input image into rectangular bins corresponding to individual pixels of the desired output image, averages pixel values in these bins, and assembles the output image from the bin averages. pixels lying on bin boundaries contribute to more than one bin average; their values are added to bin-wide sums of pixel values with fractional weights. the entire procedure preserves all image information that can be included in the do wnsized output image and filters out high frequency features that could cause aliasing. the image cropping and scaler module can be used together to implement a digital zoom and pan. if the scaler is programme d to output images smaller than images coming from the sensor core, zoom effect can be produced by cropping the latter from their maximum size down to the size of the output images. the ratio of these two sizes determines the maximum attainable zoom factor. for example, a 2560 x 1920 image rendered on a 256 x 192 display can be zoomed up to ten times, since 2560/256 = 1920/192 = 10. panning effect can be ac hieved by fixing the size of the crop- ping window and moving it around the pixel array. if downscaling by 3:1 or more, 2d aperture correction may be applied to increase image sharpness lost due to pixel binning during image scaling. yuv-to-rgb/yuv conversion and output formatting the yuv data stream emerging from the scal ing module can either exit the color pipe- line as-is or be converted before exit to an alternative yuv or rgb data format. output interface (parallel and mipi output) the user can select to either use the serial mipi output or the 8-bit parallel output to transmit the data. only one of the output modes can be used at any time. the parallel output is used with an output fifo whose memory is shared with the mipi output fifo to retain a constant pixel outp ut clock independent from the scaling factor. the mipi output transmitter implements a serial differential sub-lvds transmitter capable of up to 768 mb/s. it supports multiple formats, error checking, and custom short packets.
mt9p111_ds rev. g pub. 5/15 en 28 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description notes: 1. data will be packed as raw8 if the data type specified does not match any of the above data types. output format and timing yuv/rgb output figure 20 depicts the output timing of yuv/rg b when a scaled data stream is equalized by buffering or when no scaling takes place. the pixel clock frequency remains constant during each lv high period. figure 20: timing of full frame data or scaled data passing through the fifo yuv/rgb data ordering the mt9p111 supports swapping ycbcr mode, as illustrated in table 7. table 6: data formats supported by mipi interface data format data type yuv 422 8-bit 0x1e 565rgb 0x22 555rgb 0x21 444rgb 0x20 raw8 0x2a raw10 0x2b user-defined byte-based data (including compressed data) 0x30 0x31 0x32 0x33 table 7: ycbcr output data ordering mode data sequence default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i frame_valid line_valid pixclk d out [7:0]
mt9p111_ds rev. g pub. 5/15 en 29 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor soc description the rgb output data ordering in default mode is shown in table 8. the odd and even bytes are swapped when luma/chroma swap is enabled. r and b channels are bit-wise swapped when chroma swap is enabled. uncompressed 10-bit bypass output raw 10-bit bayer data from the sensor core ca n be output in bypass mode in two ways: ? using 8 data output signals (d out [7:0]) and vgpio[1:0]. the vgpio signals are the least significant 2 bits of data. ? using only 8 signals (d out [7:0]) and a special 8 + 2 data format, shown in table 9. table 8: rgb ordering in default mode mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 565rgb odd r 7 r 6 r 5 r 4 r 3 g 7 g 6 g 5 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3 555rgb odd 0 r 7 r 6 r 5 r 4 r 3 g 7 g 6 even g 5 g 4 g 3 b 7 b 6 b 5 b 4 b 3 444xrgb odd r 7 r 6 r 5 r 4 g 7 g 6 g 5 g 4 even b 7 b 6 b 5 b 4 0 0 0 0 x444rgb odd 0 0 0 0 r 7 r 6 r 5 r 4 even g 7 g 6 g 5 g 4 b 7 b 6 b 5 b 4 table 9: 2-byte rgb format byte bits used bit sequence odd bytes 8 data bits d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 d 1 d 0
mt9p111_ds rev. g pub. 5/15 en 30 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor jpeg encoder jpeg encoder the jpeg compression engine in the mt9p111 is a highly integrated, high-performance solution that provides for low power cons umption and full prog rammability of jpeg compression parameters for image quality control. the jpeg encoding block is designed for continuous image flow and is ideal for low power applications. after initial configurat ion for a target application, it can be controlled easily for instantaneous stop or restart. a flexible configuration and control interface allows for full programmability of various jpeg-specific parameters and tables. jpeg encoding highlights ? sequential dct (baseline) is o/iec 10918-1 jpeg-compliant ? ycbcr 4:2:2 format compression, but does not support yuv 4:2:0 output format ? support for jpeg 4:2:0 output for image widths that are less than 1280 pixels ? support for two pairs of prog rammable quantization tables ? quality/compression ratio control capability ? 15 fps jpeg capability at full resolution with or without jfif- or exif-compliant header ? support for interleaved rgb or yuv thumbnail up to 640 x 480 ? capture color pipe bypass stream (8- or 10-bit), jpeg bypass stream (16-bit), or jpeg encoded stream (8-bit), as progra mmed by host or microcontroller ? jpeg encoded stream can work in continuous mode or spoof mode ? jpeg encoded stream working in continuous mode can only transmit on the parallel output port ? thumbnail can be enabled for the jpeg encoded stream in both continuous and spoof mode ? in spoof mode, data is output with prog rammed spoof frame sizes; dummy pixels may be padded as necessary ? support for scalado speedtags ? ? mipi data types ? spoof-frame height can be ignored in spoof mode ? optional jfif or exif header generation jpeg output interface jpeg data jpeg data can be output in both the parallel and the serial mipi streams. in the parallel output interface, jpeg data is output on the 8-bit parallel bus d out [7:0], with fv, lv, and pixclk. jpeg output data is valid when both fv and lv are asserted. when the jpeg data output for the frame completes, or buffer overflow occurs, lv and fv are de- asserted. the mt9p111 can transmit jpeg data using two different formats: jpeg continuous stream and jpeg spoof stream. in both format s, jpeg status segments containing infor- mation (resolution, file size, and status) about the image and the offsets of thumbnail data can be inserted into the output stream s. the following sections describe the two streaming methods.
mt9p111_ds rev. g pub. 5/15 en 31 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor jpeg encoder rgb or ycbcr thumbnail to support display of captured images with out decoding a jpeg file, the mt9p111 can output a resized version of the captured jpeg data as an rgb or ycbcr thumbnail image embedded in the jpeg stream. this thumbnail image is computed from the same image that is input to the jpeg compressor, and is scaled to a user-progr ammable size, from 160 x 120 to 640 x 480. the thumbnail size must be configured to be at least two times smalle r than the jpeg image size. this image can be separated by parsing the stream for tags surrounding the embedded image. alternatively, the embedded image can be extracted without parsing by reading thumbnail data offsets from the thumbnail poin ter table. this thumbnail pointer table is optionally output in the image status segmen t, and contains one entry for each line of thumbnail data. note: there is a specific usage case that may produce skipped frames when used in jpeg full resolution with thumbnail mode. if spoof full height and no header, soi/eoi only with status is implemented. jpeg continuous stream jpeg continuous stream goes out only th rough the parallel output interface, and supports the following features: ? adaptive clock switching ?duplicate fv on lv ? append jpeg status segment at the end of the data stream when enabled, the pixel clock output can be generated continuously during invalid data periods (between fv and between lv). in this streaming mode, the amount of valid data within each line (lv = 1) is variable. when adaptive clock mode is enabled, the pixel clock is adjusted to lower clock rates, based on the fullness of the output fifo. figure 21 through figure 24 on page 33 are examples of the jpeg stream through the parallel output interface. figure 21 illustrates data output when the pi xel clock output is ge nerated continuously during invalid data periods. lv is of va riable length based on data output rate. in default mode, data transitions on the falling of pixclk and the host must capture data on the rising edge of pixclk. the pixclk is also configurable and its polarity can be reversed through the use of register settings. figure 21: jpeg continuous data output fv lv pixclk d out [7:0]
mt9p111_ds rev. g pub. 5/15 en 32 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor jpeg encoder notes: 1. under default conditions fv and lv are asserted on the falling edge of pixclk. 2. data must be captured by the host on the rising edge of pixclk. jpeg spoof stream the jpeg compressed data can be output in spoof mode. the amount of expected pixel data is defined by the width and height registers in spoof mode. if the valid jpeg data is less than expected size defined, a register-programmable dummy data pattern with a default value of 0xff will be padded. when enabled, the pixel clock output can be generated continuously during invalid data periods (between fv and between lv). in this streaming mode, the amount of valid data within each line (lv = 1) is constant. when adaptive clock mode is enabled, the pixel clock is readjusted to lower clock rates, base d on the fullness of the output fifo. below are some examples of the jpeg spoof stream. figure 22 illustrates the jpeg spoof output when pixel clock is generated continuously during invalid data periods between lv. the st atus segment is inserted at the end of the stream. figure 22: jpeg spoof mode timing with continuous clock notes: 1. pixclk is reversed in this example with data output on the rising edge of pixclk and data captured by the host on the falling edge of pixclk. figure 23 illustrates the jpeg spoof output when the adaptive clock mode is enabled. with continuous pixclk, the switching of the pixclk frequency can happen at any time. figure 23: jpeg spoof mode timing with adaptive clock fv lv pixclk d out [7:0] status segment dummy data fv lv pixclk d out [7:0] status segment dummy data
mt9p111_ds rev. g pub. 5/15 en 33 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor jpeg encoder notes: 1. pixclk is reversed in this example with data output on the rising edge of pixclk and data captured by the host on the falling edge of pixclk. jpeg spoof stream in mipi output mode in mipi output mode, only the jpeg spoof st ream can be output. similar to the parallel output interface, the amount of expected pi xel data is defined by the width and height registers in spoof mode. if the valid jpeg data is less than expected size defined, register-specified dummy data will be padded. jpeg stream with embedded thumbnail image in jpeg mode, it is possible to embed a scaled uncompressed image to the compressed data stream. this image is interleaved within the data (as shown in figure 24), and must be separated before saving the compressed image. the embedded image is separated from the main image by optional start of embedded image (soei) and end of embedded image (eoei) tags. these tags are register-programmable codes that enable a host to parse the thumbnail data from the compressed image stream. figure 24: jpeg spoof mo de timing wi th thumbnail notes: 1. pixclk is inverted in this example. 2. thumbnail start and end codes are programmable by register setting. 3. status segment includes jpeg pointer table. in addition, the output formatter can append a table of thumbnail data offsets to the status segment of the image. this thumbnail index pointer shall have one entry for each line of thumbnail data. each entry is a 4-byte pointer containing the offset of the valid thumbnail data. fv lv pixclk dummy data d out [7:0] jpeg data thumbnail jpeg data status segment soei eoei
mt9p111_ds rev. g pub. 5/15 en 34 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor jpeg encoder jpeg status segment to provide the user quick knowledge of the status when the jpeg plus thumbnail is enabled, a jpeg status segment is appended at the end of frame. this segment is optional in continuous mode, while it is mandatory for spoof mode.the status segment is enclosed by sosi/eosi codes, as shown in figure 25. figure 25: jpeg status segment structure the contents of the status segment are summarized as follows: ? sosi, start of status information, which is coded as 0xffbc ? thumbnail index table (every entry has 4 by tes) is asserted and thumbnail is enabled ? the width of thumbnail in pixels (2 bytes) ? the height of thumbnail (2 bytes) ? the width of uncompressed full image ? the height of uncompressed full image ? 4-byte jpeg plus thumbnail length ?2-byte status ? eosi, end of status information, which is coded as 0xffbd ? options to use to match legacy parts either thumbnail data or jpeg data starts first, depending on the time of their availability. scalado speedtags? support the mt9p111 supports scalado speedtags ? by inserting markers into the jpeg stream. this is enabled by the register bit tx _ss.jpeg_ctrl.jpeg_insert_rajpeg_markers (r0x3c40[7]. sosi on next line (optional) eosi (0xffbd) thumbnail index table height * 4 bytes (optional) thumbnail size (optional) original jpeg size 4 bytes (optional) txf status (2 bytes) frame length (4 bytes) tn 2 bytes (optional)
mt9p111_ds rev. g pub. 5/15 en 35 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor anti-shake (as) anti-shake (as) as mobile devices become smaller, unavoidable handshaking make it difficult for a user to hold a slim mobile camera steady enough to get a flawless shot, especially when expo- sure time increases due to low light conditions. to reduce motion blur, the mt9p111 includes an anti-shake mode. when motion is detected, it will increase the sensor sensi- tivity and reduce the exposure time correspondingly. the anti-shake mode will reduce the motion blur caused by camera handshaking. figure 26 shows the block diagram for the anti-shake algorithm. figure 26: anti-shake algorithm preview frames finalize af, ae, awb preview preview image capture anti-shake control adjust exposure and gain
mt9p111_ds rev. g pub. 5/15 en 36 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control camera control general purpose i/os the eight general purpose i/os of the mt9p111 can be configured in multiple ways. each of the i/os can be used for multiple purposes and can be programmed from the host. the vgpios are powered by their own power supply domain. the vgpio configu- rations are shown in table 10. if the auto-focus mechanisms ar e controlled by the serial master, all eight vgpios will be available for advanced flash and mechanical shutter operations. the general purpose inputs are enabled or disabled through register settings. the state of the general purpose inputs can be read from a register. output enable control when the parallel pixel data interface is en abled, its signals can be switched asynchro- nously between the driven and high-z under pin or register control. trigger control when the global reset feature is in use, the trigger for the sequence can be initiated either under pin or register control. table 10: vgpio configurations vgpio[7:0] standard configuration w/ vgpio as inputs standard configuration w/ vgpio as outputs optional configuration w/ vgpio as inputs and sensor core not needed optional configuration w/ vgpio as outputs and sensor core not needed default vgpio[0] shutter_sel dout_lsb[0] gpi gpo_pwm gpi vgpio[1] flash_sel dout_lsb[1] gpi gpo_pwm gpi vgpio[2] oe_bar shutter gpi gpo_pwm gpi vgpio[3] gpi flash gpi gpo_pwm gpi vgpio[4] gpi gpo_pwm gpi gpo_pwm gpi vgpio[5] gpi gpo_pwm gpi gpo_pwm gpi vgpio[6] gpi gpo_pwm gpi gpo_pwm gpi vgpio[7] gpi gpo_pwm gpi gpo_pwm gpi table 11: trigger control gpi configured trigger pin global trigger description disabled 0 idle disabled 1 trigger 00idle x 1 trigger 1 x trigger
mt9p111_ds rev. g pub. 5/15 en 37 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control firmware architecture the firmware for the mt9p111 is implemented in multiple drivers that are responsible for different parts of operation. figure 27: firmware architecture block diagram sequencer the sequencer is responsible for coordinating all events triggered by the user. it is imple- mented as a state machine. for example, sending a capture command to the sequencer will change the resolution from preview to full resolution, turn on or off an external led, and switch back to preview after capturing the frame. the setup of the sensor can be defined by the user for preview and capture. monitor sequencer af mechanics auto focus operation driver auto function driver control driver hardware auto exposure auto white balance flicker avoidance camera configuration ram vgpio stat ifp sensor core output camera control anti- shake jpeg control flash control
mt9p111_ds rev. g pub. 5/15 en 38 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control context and operational modes the mt9p111 can operate in several modes including preview, still capture (snapshot), and full resolution video. all modes of oper ation are individually configurable and are organized as two contexts?context a and co ntext b. context switching can be accom- plished by sending a command throug h the two-wire serial interface. preview mode context a is primarily intended for use in th e preview mode. during preview, the sensor usually outputs low resolution images at a relatively high frame rate, and its power consumption is kept to a minimum. all automa tic functions are enabled in this mode to adjust to the best image possible. still capture and video modes context b can be configured for the full resolution still capture or video mode, as required by the user. for still capture configuration, the user typically specifies the desired output image size, if flash should be enabled, how many frames to capture, and so forth. for video, the user might select a different image size and a fixed frame rate. snapshot and flash to take a snapshot, the user must send a co mmand that changes the context from a to b. a typical sequence of events after this command is: 1. the camera may turn on its led flash, if it has one and is required to use it. with the flash on, the camera exposure and white balance are automatically adjusted to the changed illumination of the scene. 2. the camera captures one or more frames of desired size. a camera equipped with a xenon flash strobes while capturing images. when capturing images is completed, the camera automatically returns to context a and resumes running in preview mode. note: this sequence of events can take up to 10 frames. video to start video capture, the user must change relevant context b settings, such as capture mode, image size and frame rate, and again send a context change command. upon receiving it, the mt9p111 switches to the mo dified context b settings, while continuing to output yuv-encoded image data. ae ad justs automatically and provides a smooth continuous operation. to exit the video capture mode, the user must send another context change command, causing the se nsor to switch back to context a. multi-shot image capture mode the mt9p111 can support multi-shot image ca pture mode (batch capture) this mode allows the user to monitor full resolution im ages, then select a series of images with short intervals to be captured by continually storing full-scale images in a ring buffer (in the customer system) to allow the user to se lect the optimal image that occurred, before, or after the capture moment.
mt9p111_ds rev. g pub. 5/15 en 39 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control auto exposure the auto exposure algorithm performs automatic adjustments of the image brightness by controlling exposure time and analog gains of the sensor core as well as digital gains applied to the image. auto exposure is implemented by a firmware driver that analyz es image st atistics collected by the exposure measurement engine, makes a decision, and programs the sensor core and color pipeline to achieve the desired exposure. the measurement engine subdivides the image into a 5 x 5 grid. the available ae options are described in the ae_rule variables (variable page 9). the average brightness tracking ae uses a co nstant average tracki ng algorithm where a target brightness value is compared to a curr ent brightness value, and the gain and inte- gration time are adjusted accordingly to meet the target requirement. continuous ae can add weighting to the ae zone s such that the center of edge (backlight compensation)-based options are available. in addition, the statistics window can be adjusted to focus on an area of interest. ae driver the auto exposure mode is activated during preview. this mode can also be enabled during video capture mode. it relies on the statistics engine that tracks speed and ampli- tude of the change of the overall luminance in the selected windows of the image. backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. other algorithm features include the rejection of fast fluctuations in illumina tion (time averaging), control of speed of response, and control of the sensitivity to the small changes. while the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters described above. the driver changes ae parameters (integration time, gains, and so on) to drive bright- ness to the programmable target. the value of the single step approach to the target value can be controlled. to avoid unwanted reaction of ae on small fluctuations of scene brightness or momen- tary scene changes, the ae driver uses a temporal filter for luma and a threshold around the ae luma target. the driver changes ae parameters only if the buffered luma is larger than the ae target step and push es the luma beyond the threshold. accelerated settling during overexposure the ae speed is direction-dependent. transi tioning from oversaturation to target can take more time than transitioning from unde rsaturation. the ae driver has a mode that speeds up ae for overexposed scenes. the ae driver counts the number of ae wind ows whose average brightness is equal to or greater than some value, 250 by default. for a scene having saturated regions, the average luma is underestimated due to sign al clipping. the driver compensates under- estimation by a factor that can be defined. exposure control to achieve the required amount of exposure, the ae driver adjusts the sensor integration time, gains, adc reference, and ifp digital gains. in addition, a variable is available for the user to adjust the overall brightness of the scene. to reject flicker, integration time is
mt9p111_ds rev. g pub. 5/15 en 40 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control typically adjusted in increments of steps. th e incremental step specifies the duration in row times equal to one flicker period. thus, flicke r is rejected if integration time is kept a natural factor of the flicker period. auto white balance the mt9p111 has a built-in auto white balance algorithm designed to compensate for the effects of changing spectra of the scen e illumination on the quality of the color rendition. the algorithm consists of two ma jor parts: a measurement engine performing statistical analysis of the image and a driv er performing the selection of the optimal color correction matrix, digital, and sensor core analog gains. while default settings of these algorithms are adequate in most situations, the user can reprogram base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. for optima l image quality, on semiconductor recom- mends keeping the analog values less than 2. flicker detection flicker occurs when the integration time is not an integer multiple of the period of the light intensity. the automatic flicker detection block does not compensate for the flicker, but rather avoids it by detecting the flicke r frequency and adjusting the integration time. for integration times below the light intens ity period (10ms for 50hz environment), flicker cannot be avoided. flicker shows as horizontal bars rolling up or down. auto focus overview the auto focus (af) algorithm implemented in the mt9p111 firmware seeks to maxi- mize sharpness of vertical lines in images output by the sensor by guiding an external lens actuator to the position of best lens fo cus. the algorithm is ac tuator-independent; it provides guidance by means of an abstract one-dimensiona l position variable, leaving the translation of its changes into physical lens movements to a separate af mechanics (afm) driver. the af algorithm relies on the afm driver to generate digital output signals needed to move different lens actuator s and to correctly indicate at all times if the lens is stationary or moving. the latter is required to prevent the af algorithm from using line sharpness measurements distorted by concurrent lens motion. for measuring line sharpness, the af algorithm relies on the focus measurement engine in the color pipeline, which is a programmable vertical-edge-filtering module. in every interpolated image, statistics are collected in 16 equal-sized rectangular sub-blocks, referred to as af windows or zones. there are several motion sequences throug h which the mt9p111 af algorithm can bring a lens to best focus position. all these sequences begin with a jump to a preselected start position, for example, the infinity focus position. this jump is referred to as the first flyback. it is followed by a unidirectional seri es of steps that puts the lens at up to 19 preselected positions different from the start position. this series of steps is called the first scan. before and during this scan, the af algorithm stops the lens at each preselected position long enough to obtain valid sharpness scores. the first normalized score from each af window is stored as both the worst (minimum) and best (maximum) score for that window. these two extreme scores are then up dated as the lens moves from one position to the next and a new maximum position is memorized at every update of the maximum
mt9p111_ds rev. g pub. 5/15 en 41 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control score. in effect, the preselected set of lens positions is scanned for maxima of the normalized sharpness scores, while at the sa me time information needed to validate each maximum is being collected. modes there are two af camera modes that the mt9p 111 can fully support if it controls the position of the camera lens. snapshot mode in this mode, a camera performs auto focusing upon a user command to do so. when the auto focusing is finished, a snapshot is normally taken and there is no further af activity until the next appropriate user command. the mt9p111 can do the auto focusing using its built-in af algorithm or a substitute algorithm loaded into ram. it can then wait or automatically proceed with other operations required to take a snapshot. manual mode in this mode there is no af activity?focusing the camera is left to the user. the user typically can move the camera lens in steps, by manually issuing commands to the lens actuator, and observing the effect of his ac tions on a preview display. the mt9p111 can provide 30 fps image input for the display and simultaneously translate user commands received through the two-wire serial interf ace into digital waveforms driving the lens actuator. lens actuator interface actuators used to move lenses in af cameras can be classified into several broad catego- ries that differ significantly in their requirements for driving signals. these requirements also vary from one device to another within each category. to ensure its compatibility with many different actuators, the mt9p1 11 includes a general purpose input/output auto focus module. the vgpio is a programmable rectangular waveform generator, with eight individually controllable output signals (vgpio0 through vgpio7), a separate power supply pad (v dd _vgpio), and a separate clock domain that can be disconnected from the master clock to save power when the vgpio is not in use. the vgpio can toggle its output signals as fast as half the master clock frequency. an external host processor or the embedde d microcontroller of the mt9p111 has two ways to control the voltages on the vgpio output signals: ? setting or clearing bits in a control register the state of the vgpio signals is updated immediately after writing to the register. because writing through the two-wire serial interface takes some time, this way does not give the host processor a very precise control over vgpio output timing. ? waveform programming the second way to obtain a desired output fr om the vgpio is to program a set of peri- odic waveforms to the control registers and initialize their generation. the vgpio then generates the programmed waveforms on its own, without waiting for any fur- ther input, and therefore with the best atta inable timing precision. if necessary, the vgpio can notify the mcu and the host proc essor about reaching certain points in the waveforms generation, for example, the end of a particular waveform. the mt9p111 can be set up not only to output digital signals to a lens actuator and/or other similar devices, but also to receive their digital feedback. all vgpio output signals are reconfigurable as high-impedance digital inputs. the logical state of each vgpio pad
mt9p111_ds rev. g pub. 5/15 en 42 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control is mirrored by the state of a bit in a dedica ted register, which allows the mcu and host processor to sample digital input signals at intervals equal to their respective register read times. in addition, the mt9p111 has an additional serial master available for use (s_clk, s_dat). it may be implemented in such a way that if the auto-focus mechanisms are controlled by the serial master, all eight vgpios would be available for advanced flash and mechan- ical shutter operations. internal vcm driver the mt9p111 utilizes an internal voice coil motor (vcm) driver. the vcm functions are register-controlled through the serial interface. there are two output ports, vcm_out and gndio_vcm, which would connect directly to the af actuator. take precautions in the design of the power supply routing to provide a low impedance path for the ground return. appropriate filter ing would also be required on the actuator supply. typical values would be a 0.1 ? f and 10 ? f in parallel. figure 28: vcm driver typical diagram table 12: vcm driver typical characteristic parameter minimum typical maximum units vcm_out voltage at vcm current sink 2.5 2.8 3.3 v wvcm voltage at vcm actuator 2.5 2.8 3.3 v inl relative accuracy 1.5 4lsb res resolution 8 bits dnl differential nonlinearity C1 +1 lsb ivcm output current 5 100 ma slew rate .3 ma/ ? s mt9p111 vcm_out gndio_vcm vcm dgnd vvcm 10 f
mt9p111_ds rev. g pub. 5/15 en 43 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor camera control user -accessible internal adc the mt9p111 provides access to an intern al 12-bit adc for customer use. the adc provides sampling, correction, and filtering. one application for the internal adc is to use as an interface to components that require analog feedback support. the access to th e internal adc is through the atest0/1 pins and the data is accessible through the serial interface. refer to the developer guide for details. multimaster serial interface the mt9p111 provides, in addition to the standard serial interface (s data , sclk), a secondary master to receive read and wr ite commands from an external host and execute the commands to the attached slave devices through the s_sclk and s_data pins. these could be used for any number of uses to control external slave components such as eeprom, autofocus, mechanic al shutter, and flash drivers.
mt9p111_ds rev. g pub. 5/15 en 44 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor two-wire serial interface two-wire serial interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the mt9p111. this interface is desi gned to be compatible with the mipi alli- ance standard for camera serial interfac e 2 (csi-2) 1.0, which uses the electrical characteristics and transfer protocols of th e two-wire serial interface specification. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (sclk) that is an input to the sens or and used to synchronize transfers. data is transferred between the master an d the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol dete rmines which device is allowed to drive s data at any given time. the mt9p111 is a multi-master device. a separate serial master is provided for the control of external components. th ese are the s_clk and s_dat pins. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements, as follows: ? a start or restart condition ? a slave address/data direction byte ? a 16-bit register address ? an acknowledge or a no-acknowledge bit ?data bytes ? a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while sclk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the mt9p111 are 0x78 (write address) and 0x79 (read address). alternate slave addresses of 0x7a (write addres s) and 0x7b (read address) can be selected by asserting the s addr input signal.
mt9p111_ds rev. g pub. 5/15 en 45 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor two-wire serial interface message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the two-wire serial interface specification. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when sclk is low and must be stable while sclk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transf er. a no-acknowledge bit is used to termi- nate a read sequence. stop condition a stop condition is defined as a low -to-high transition on s data while sclk is high. typical serial transfer a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then tr ansfers the 16-bit register address to which a write should take place. this transfer take s place as two 8-bit sequences and the slave sends an acknowledge bit after each sequen ce to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends acknowledge bit at the end of the sequence. afte r 8 bits have been transferred, the slave?s internal register address is automatically incr emented, so that the next 8 bits are written to the next register address. the master st ops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the mast er generates an acknowledge bit after each 8- bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowl- edge bit. note: if a customer is using direct memory writes (xdma), and the first write ends on an odd address boundary and the second writ e starts on an even address boundary and the first write is not terminated by a stop, the write data can become corrupted. to avoid this, ensure that a serial write is terminated by a stop.
mt9p111_ds rev. g pub. 5/15 en 46 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor two-wire serial interface single read from random location this sequence (see figure 29) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 29 shows how the internal register address maintained by the mt9p111 is loaded and incremented as the sequence proceeds. figure 29: single read from random location single read from current location this sequence (figure 30) performs a read using the current value of the mt9p111 internal register address. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 30: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l a read data slave address a a 1 read data a s s
mt9p111_ds rev. g pub. 5/15 en 47 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor two-wire serial interface sequential read, start from random location this sequence (figure 31) starts in the same way as the single read from random location (figure 29). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until l by tes have been read. figure 31: sequential read, start from random location sequential read, start from current location this sequence (figure 32) starts in the same way as the single read from current location (figure 30). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until l by tes have been read. figure 32: sequential read, start from current location single write to random location this sequence (figure 33) begins with the ma ster generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. th e master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 33: single write to random location slave address 0 s sr a reg address[15:8] a read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a 1 a a read data read data m+l-2 m+l-1 m+l a s a read data read data previous reg address, n n+1 n+2 n+l-1 n+l a read data slave address a a 1 read data a s s slave address 0 s a reg address[15:8] a reg address[7:0] a write data p previous reg address, n reg address, m m+1 a a
mt9p111_ds rev. g pub. 5/15 en 48 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor two-wire serial interface sequential write, start at random location this sequence (figure 34) starts in the same way as the single write to random location (figure 33). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte writes until l bytes have been written. the write is terminated by the master gener- ating a stop condition. figure 34: sequential write, start at random location slave address 0 s a reg address[15:8] a write data write data a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a write data write data m+l-2 m+l-1 m+l a a s
mt9p111_ds rev. g pub. 5/15 en 49 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications timing specifications power-up sequence powering up the sensor is independent of voltages applied in a particular order, as shown in figure 35. the timing requirements fo r other signals are shown in table 13. it is advised that the user manually as sert a hard reset upon power up. caution applying power to analog supplies prior to applying digital and io supplies follow the cor- rect power-up sequence may result in high cu rrent consumption this can potentially result in performance and reliability issues. figure 35: power-up sequence notes: 1. all supplies are referenced to v dd . 2. outputs will be in high z st ate while reset_bar is asserted. table 13: power-up signal timing parameter symbol min typ max unit v dd to v dd _io t 10C500 ms v dd to v dd _pll t 20C500 v dd to vaa_pix t 30C500 v dd to extclk activation t 41500C reset_bar activation time t 570CCextclks first serial write t 6100C Cextclks t 1 t 2 t 3 t 4 t 5 t 6 v dd v dd _io v dd _pll vaa_pix, v aa extclk reset_bar sclk s data first serial write
mt9p111_ds rev. g pub. 5/15 en 50 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications power-down sequence figure 36 shows the recommended powe r-down sequence for the mt9p111. figure 36: power-down sequence note: outputs will be in high z state while reset_bar is asserted. the best condition for the power down would be turning all the power supplies down at the same time. table 14 shows the minimum conditions for power-down sequence. table 14: power-down sequence parameter symbol min typ max unit hard reset t 11CCms v aa , vaa_pix to v dd , v dd _mipi time t 20CCms v dd _pll to v dd , v dd _mipi time t 30CCms v dd , v dd _mipi to v dd _io time, t 40CCms
mt9p111_ds rev. g pub. 5/15 en 51 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications reset two types of reset are available: ? a hard reset is issued by toggling reset_bar. ? a soft reset is issued by writing commands through the two-wire serial interface. hard reset after hard reset, the output fifo is configur ed for operation but disabled and all outputs are tri-stated. these outputs can be enabled th rough the two-wire seri al interface. after hard reset, the output fifo is configured for operation but disabled and all outputs are tri-stated. these outputs can be enabled through the two-wire serial interface. the hard reset signal sequence is shown in figure 37 on page 51. hard reset timing is shown in table 15 on page 51. figure 37: hard reset signal sequence note: the mt9p111 does not suppor t the special usage case where v aa = 0 and v dd io_tx = 2.8v during reset. higher leakage currents will occur while reset_bar = 0. soft reset a soft reset sequence to the sensor has the same affect as the hard reset and can be acti- vated writing to a register through the two-wi re serial interface. the soft reset signal sequence is shown in figure 38. soft reset ti ming is shown in table 16 on page 52. stan- dard start-up procedures will need to be followed after a soft reset. table 15: hard reset signal timing parameter symbol min typ max unit reset_bar pulse width t 170CCextclks active ecxtclk after reset_bar is asserted t 210CC active extclk before reset_bar is de- asserted t 310CC first two-wire serial interface communication after reset is high t 4 C 100 C extclk t 1 t 2 t 3 t 4 reset_bar s data mode reset m3 rom read standby / first serial write allowed
mt9p111_ds rev. g pub. 5/15 en 52 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications figure 38: soft reset signal sequence table 16: soft re set signal timing parameter symbol min typ max unit active extclk after soft reset command is asserted t 1 C120Cextclks extclk t 1 sdata mode write soft reset command reseting registers registers reset to default values sclk
mt9p111_ds rev. g pub. 5/15 en 53 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications standby modes the mt9p111 supports the following standby modes: ?hard standby ? soft standby with state retention for hard and soft standby modes, entry can be inhibited by programming the standby_- control register. to optimize low leakage in standby, a controlled extclk signal mst be used without overshoot. hard standby mode the hard standby mode uses standby to shut down digital power (v dd ) and enter low power standby mode. the host will not have to reload the pll, clock divider settings, and patches but other sensor settings such as context settings, lsc, ccm, and so forth will have to be reloaded. the two-wire serial interface will be inactive and the sensor must be started up by de-asserting standby. during standby, only the sysctrl regis- ters are safely accessible. the signal sequence is shown in figure 39. the timing is shown in table 17. figure 39: hard standby signal sequence mode table 17: hard standby signal timing parameter symbol min typ max unit standby entry complete t 120CC ? s active extclk before standby de-asserted t 210CC standby pulse width t 3100C C standby de-assertion to first allowable serial write t 420CC extclk standby mode t 1 t 3 t 2 standby asserted extclk disabled extclk enabled
mt9p111_ds rev. g pub. 5/15 en 54 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications soft standby with state retention soft standby with state retention can be en abled by register access and disables the sensor core and most of the digital logic. the two-wire serial interface is still active and the sensor can be programmed through register commands. all register settings and ram content will be preserved. soft standby can be performed in any sequencer state after all ae, awb, histogram, an d flicker calculations are fini shed and the sensor core has been disabled. the execution of standby will take place after the completion of the current line by default. it is possible to synchronize the execution of standby with the end of frame through the standby_control register. the so ft standby signal sequence is shown in figure 40. the timing for the signals is shown in table 18. figure 40: soft standby signal sequence shutdown mode the shutdown mode is entered when the shutdown pin is asserted. all power to the mt9p111 is disabled and no state, register or patch information is retained. de-assertion of the shutdown pin will cause a full por. note: the mt9p111 does not support the special usage case where v aa = 0 and v dd io_tx = 2.8v during shutdown. this will cause higher leakage currents to occur. refer to the mt9p111 errata document for special usage notes on hard standby and shutdown modes. table 18: soft standby signal timing parameter symbol min typ max unit standby entry complete t 120CC s active extclk before soft standby de- activates t 210CC minimum standby time t 3100C C extclk r0x0018[0] mode t 1 t 2 t 4 t 3 poll r0x0018[14] standby mode extclk disabled extclk enabled set r0x0018[0] = 1 sdata r0x0018[14] = 1
mt9p111_ds rev. g pub. 5/15 en 55 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications table 19: dc electrical definitions and characteristicsparallel mode f extclk = 24 mhz; f pixclk = 96 mhz; v dd = 1.8v; v dd _io = 1.8v or 2.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; v dd io_tx = 2.8v; t j = 70c; refer to power reduction modes for descriptions of low power and dynamic power modes. symbol parameter condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io1 i/o digital voltage at 1.8v option 1.7 1.8 1.95 v v dd _io2 i/o digital voltage at 2.8v option 2.5 2.8 3.1 v v aa analog voltage 3 2.5 2.8 3.1 v vaa_pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v i dd digital operating current context a (vga, ycbcr, 10-bit) low power mode (r0x3040[9] = 1) C56Cma i aa analog operating current context a C 76 C ma i aa _pix pixel supply current context a C 5 C ma i dd _pll pll supply current context a C 22 C ma i dd io_mipi mipi supply current context a C 4 C ma total supply current context a C 163 C ma total power consumption context a C 401 C mw i dd digital operating current context a (vga,ycbcr,10-bit) high power mode (r0x3040[9] = 0) with dynamic power mode asserted C74Cma i aa analog operating current context a C 64 C ma i aa _pix pixel supply current context a C 7 C ma i dd _pll pll supply current context a C 17 C ma i dd io_mipi mipi supply current context a C 4 C ma total supply current context a C 166 C ma total power consumption context a C 389 C mw i dd digital operating current context a (vga,ycbcr,10-bit) low power mode (r0x3040[9] = 1) with dynamic power mode asserted C54Cma i aa analog operating current context a C 26 C ma i aa _pix pixel supply current context a C 5 C ma i dd _pll pll supply current context a C 21 C ma i dd io_mipi mipi supply current context a C 4 C ma total supply current context a C 110 C ma total power consumption context a C 253 C mw i dd digital operating current context b (full resolution jpeg, 10 bit) high power mode (reg 0x3040[9] = 0) with dynamic power mode asserted C120C ma
mt9p111_ds rev. g pub. 5/15 en 56 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications notes: 1. context a: 30 fps preview yuv mode. 2. context b: 15 fps full resolution jpeg mode. 3. in standby mode, vaa should not be grounded 4. to optimize low leakage state in standby, a controlled extclk signal must be used without over- shoot i aa analog operating current context b C 98 C ma iaa_pix pixel supply current context b C 10 C ma i dd _pll pll supply current context b C 20 C ma i dd io_tx mipi supply current context b C 4 C ma total supply current context b C 252 C ma total power consumption context b C 586 C mw hard standby total standby current when asserting the standby signal v dd disable on r0x0028[0] = 1 (t j = 70c) 10 ? a hard standby total standby current when asserting the standby signal v dd disable off r0x0028[0] = 0 (t j = 70c) 300 ? a soft standby (clock on at 24 mhz) total standby current when asserting r0x0018[0] = 1 v dd disable on r0x0028[0] = 1 550 ? a soft standby (clock on at 24 mhz) total standby current when asserting r0x0018[0] = 1 v dd disable off r0x0028[0] = 0 8500 ? a soft standby (clock off) total standby current when asserting r0x0018[0] = 1 v dd disable on r0x0028[0] = 1 10 ? a soft standby (clock off) total standby current when asserting r0x0018[0] = 1 v dd disable off r0x0028[0] = 0 300 ? a shutdown (clock on) total standby current when asserting the shutdown signal at maximum voltage and clock running 10 ? a table 19: dc electrical definitions and characteristicsparallel mode (continued) f extclk = 24 mhz; f pixclk = 96 mhz; v dd = 1.8v; v dd _io = 1.8v or 2.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; v dd io_tx = 2.8v; t j = 70c; refer to power reduction modes for descriptions of low power and dynamic power modes. symbol parameter condition min typ max unit
mt9p111_ds rev. g pub. 5/15 en 57 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications note: high speed parameters are not included. figure 41: i/o timing diagram notes: 1. fv leads lv by 6 pixclks. 2. fv trails lv by 6 pixclks. 3. pll disabled for t cp table 20: i/o parameters symbol parameter conditions min typ max unit v ih input high voltage at specified i in v dd _io C 0.4 v dd _io + 0.3 v v il input low voltage v dd _io = 2.8v at specified i in C0.3 0.6 v v dd _io = 1.8v at specified i in C0.3 0.4 v i in input leakage current no pull-up resistor; v in = v dd or d gnd C10 10 ? a v oh output high voltage at specified i oh v dd _io C 0.4 C v v ol output low voltage at specified i ol C0.4v i oh output high current at minimum of 1.4v v oh CC13ma at minimum of 2.4v v oh CC20ma i ol output low current at maximum of 0.4v v ol C12ma at specified v ol C15ma i oz tri-state output leakage current 5 ? a extclk pixclk t r t f t extclk d out [7:0] frame_valid/ line_valid xxx xxx xxx xxx xxx xxx t cp t pfl t pll t pd t pd t pfh t plh data data data data data 90% 10% note 1 note 2
mt9p111_ds rev. g pub. 5/15 en 58 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications notes: 1. measured in terms of standard deviation. 2. from falling edge of pixclk. 3. pll disabled for t cp. 4. pixclk = 24 mhz. table 21: i/o timing specifications f extclk = 24 mhz; f pixclk = 96 mhz; v dd = 1.8v; v dd _io = 1.8v or 2.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; v dd io_tx = 2.8v; t j = 70c symbol parameter conditions min typ max unit note f extclk external clock frequency 10 C 48 mhz t extclk external clock period 20.8 100 ns extclk duty cycle 45 50 55 % t r extclk rise time (for pll bypass mode) 0.05 * t extclk ns t f extclk fall time (for pll bypass mode) 0.05 * t extclk ns t jitter extclk jitter (peak-peak cycle jitter) C 0.5 1 ns 1 t cp extclk to pixclk propagation delay ns 3 f pixclk pixclk frequency default 6 C 96 mhz t rpixclk pixclk rise time c load = 15pf C 2 5 ns t fpixclk pixclk fall time c load = 15pf C 2 5 ns t pd pixclk to data valid default 0.4 * t pixclk 0.5 * t pixclk 0.6 * t pixclk ns 2 t pfh pixclk to fv high default 0.4 * t pixclk 0.5 * t pixclk 0.6 * t pixclk ns 2 t plh pixclk to lv high default 0.4 * t pixclk 0.5 * t pixclk 0.6 * t pixclk ns 2 t pfl pixclk to fv low default 0.4 * t pixclk 0.5 * t pixclk 0.6 * t pixclk ns 2 t pll pixclk to lv low default 0.4 * t pixclk 0.5 * t pixclk 0.6 * t pixclk ns 2 pixclk signal slew r0x001e[10:8] = 000 v dd _io: typ c load = 45pf 0.21 v/ns 4 r0x001e[10:8] = 100 v dd _io: typ c load = 45pf 0.66 v/ns 4 r0x001e[10:8] = 111 v dd _io: typ c load = 45pf 1.2 v/ns 4 d out [7:0] signal slew r0x001e[2:0] = 000 v dd _io: typ c load = 45pf 0.21 v/ns 4 r0x001e[2;0] = 100 v dd _io: typ c load = 45pf 0.66 v/ns 4 r0x001e[2;0] = 111 v dd _io: typ c load = 45pf 1.2 v/ns 4 c in input pin capacitance C 2.5 C pf r in input pin impedance C 400 C k ?
mt9p111_ds rev. g pub. 5/15 en 59 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications two-wire serial bus timing figure 42 and table 22 on page 60 describe the timing for the two-wire serial interface. figure 42: two-wire serial bus timing parameters
mt9p111_ds rev. g pub. 5/15 en 60 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications table 22: two-wire seri al bus characteristics f extclk = 10C48 mhz; v dd = 1.8v; v dd _io = 1.8v or 2.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; v dd _phy = 2.8v; t j = 70c symbol parameter conditions min typ max unit note f sclk serial interface input clock frequency 100 C 400 khz t sclk serial interface input clock period 2.5 C 10 ps master clock cycle units or pll cycles if enabled sclk duty cycle 40 50 60 % t srth start hold time write/read 0.3 C C ? s master clock cycle units or pll cycles if enabled t sdh s data hold write 0.3 C C ? s master clock cycle units or pll cycles if enabled t sds s data setup write 0.3 C C ? s master clock cycle units or pll cycles if enabled t shaw s data hold to ack write 0.15 C 0.75 ? s master clock cycle units or pll cycles if enabled t ahsw ack hold to s data write 0.3 C C ? s master clock cycle units or pll cycles if enabled t stps stop setup time write/read 0.3 C C ? s master clock cycle units or pll cycles if enabled t stph stop hold time write/read 0.6 C C ? s master clock cycle units or pll cycles if enabled t shar s data hold to ack read 0.15 C 0.75 ? s master clock cycle units or pll cycles if enabled t ahsr ack hold to s data read 0.15 C 1 ? s master clock cycle units or pll cycles if enabled t sdhr s data hold read 0.3 C C ? s master clock cycle units or pll cycles if enabled t sdsr s data setup read 0.3 C C ? s master clock cycle units or pll cycles if enabled c in_si serial interface input pin capacitance CC 3.3 pf c load_sd s data max load capacitance C C 30 pf r sd s data pull-up resistor C 1.5 C k ?
mt9p111_ds rev. g pub. 5/15 en 61 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications caution table 23 shows stress ratings only, and functi onal operation of the device at these or any other conditions above those indicated in the product specification is not implied. stresses above those listed may cause permanent damage to the device. exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. table 23: absolute maximum ratings symbol parameter rating unit min max v dd _max core digital voltage C0.3 2.4 v v dd _io_max i/o digital voltage C0.3 4.0 v v aa _max analog voltage C0.3 4.0 v vaa_pix_max pixel supply voltage C0.3 4.0 v v dd _pll_max pll supply voltage C0.3 4.0 v v ih _max input high voltage v dd _io + 0.3 v v il _max input low voltage C0.3 v t_op operating temperature (measured at junction) C30 75 c t_st storage temperature C40 85 c
mt9p111_ds rev. g pub. 5/15 en 62 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications one-time programmable memory programming sequence figure 43 shows the sequence of signals to be used for otp memory programming sequence. the supply voltages and extclk to be used are shown in table 24 on page 63. figure 43: sequence of signals for otp memory operation note: there is a one-time programmable memory timing calculator available for customer use. please contact on semiconductor engineering support. reset_bar extclk sclk/s data v pp power supplies information to be programmed to the register initiate programming and poll status bit read programmed values for status
mt9p111_ds rev. g pub. 5/15 en 63 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor timing specifications signal states note: x = dont care. table 24: supplies voltages and clock frequency for otp memory programming symbol parameter min typ max unit f clkin input clock frequency 10 12 48 mhz v dd core digital voltage 1.8 v v dd _io i/o digital voltage 1.8 or 2.8 v v aa analog voltage 2.6 2.8 3.1 v vaa_pix pixel supply voltage 2.8 v v dd _pll pll supply voltage 2.8 v v pp programming voltage 8.5 v v dd io_tx mipi supply voltage 2.8 v table 25: status of signals during different states signal reset post-reset standby standby with shutdown power down d out [7:0] high-z high-z high-z by default (configurable via oe_bar or two-wire serial interface reg) high-z by default x pixclk high-z high-z high-z by default (configurable) high-z by default x lv high-z high-z high-z by default (configurable) high-z by default x fv high-z high-z high-z by default (configurable) high-z by default x dout_n 0 0 0 0 x dout_p 0 0 0 0 x clk_n 0 0 0 0 x clk_p 0 0 0 0 x vgpio[7:0] high-z high-z depending on how system uses them depending on how system uses them x s addr input input input input s data input i/o input input sclk input input input input s_scl high-z high-z high-z by default (configu rable) high-z by default (configurable) x s_sda input i/o input input
mt9p111_ds rev. g pub. 5/15 en 64 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor spectral characteristics spectral characteristics note: on semiconductor recommends the use of a 670 nm ir cut filter for the mt9p111 for improved performance. figure 44: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 000 5 0.113 2.19 10 0.227 4.33 15 0.340 6.43 20 0.454 8.50 25 0.567 10.55 30 0.680 12.57 35 0.794 14.52 40 0.907 16.39 45 1.021 18.15 50 1.134 19.76 55 1.247 21.20 60 1.361 22.43 65 1.474 23.44 70 1.588 24.21 75 1.701 24.74 80 1.814 25.03 85 1.928 25.11 90 2.041 25.01 95 2.155 24.80 100 2.268 24.55 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100110 image height (%) cra (deg)
mt9p111_ds rev. g pub. 5/15 en 65 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor revision history revision history rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/5/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template ? removed confidential marking rev e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/11/10 ? updated figure 31: ?sequential read, st art from random location,? on page 47 ? updated figure 32: ?sequential read, start from current location,? on page 47 ? updated figure 34: ?sequential write, start at random location,? on page 48 ?updated ?standby modes? on page53 ? updated table 19, ?dc electrical definition s and characteristics?parallel mode,? on page 55 ? updated table 21, ?i/o timing specifications,? on page 58 ? updated figure 42: ?two-wire serial bus timing parameters,? on page 59 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/11/10 ? updated to production ? updated the following parameters in table 1, ?key performance parameters,? on ? page 1: ?snr max ?responsivity ?power consumption ? updated descriptions for standby, shutdown, vgpio[7:0], v dd _vgpio and gnd_vgpio in table 3, ?signal descriptions,? on page 8 ? updated note 8 for figure 1: ?typical configuration (connection),? on page 9 ? added first paragraph and updated note 7 in ?decoupling capacitor recommenda- tions? on page 10 ? updated recommended maximum analog value in ?auto white balance? on page 40 ? added caution to ?power-up sequence? on page 49 ? added last paragraph to ?shutdown mode? on page 55 ? updated parameter column for t r and t f in table 21, ?i/o timing specifications,? on page 59 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/11/09 ? updated to aptina imaging corporation template ? deleted ?with dithering? from ?features? on page 1 ? changed rajpeg to speedtags ? throughout document ? updated table 1, ?key performance parameters,? on page 1 ? changed dynamic range to 62db ? changed responsivity to 0.64 v/lux-sec ? changed i/o supply voltage to ?1.7-1.9v or 2.5?3.1v? ? deleted last sentence of 2nd paragr aph in ?mt9p111 overview? on page 6 ? updated table 3, ?signal descriptions,? on page 7 ? updated descriptions of extclk and d out [7:0] ? updated item 2 in ?decoupling capacitor recommendations? on page 10 ? deleted 2nd sentence in ?pll-generated clocks? on page 14
mt9p111_ds rev. g pub. 5/15 en 66 ?semiconductor components industries, llc, 2015. mt9p111: 1/4-inch 5 mp soc digital image sensor revision history ? added 3rd sentence in ?pll setup? on page 14 ? deleted pmb3 in ?binning? on page 19 ? added ?power reduction modes? on page 21 ? added last two sentences in?one-time programmable memory? on page 25 ? updated ?jpeg encoding highlights? on page 30 ? added note to ?rgb or ycbcr thumbnail? on page 31 ? added ?scalado speedtags? support? on page 34 ? deleted bullets in ?multi-shot image capture mode? on page 38 ? updated ?auto exposure? on page 39 ? added last sentence in ?auto white balance? on page 40 ? updated ?user -accessible internal adc? on page 43 ? updated ?multimaster seri al interface? on page 43 ? updated heading of ?two-wire serial interface? on page 44 ? added note to ?typical serial transfer? on page 45 ? removed register tables (moved to separate document) ? updated table 13, ?power-up signal timing,? on page 49 ? added ?power-down sequence? on page 50 ? updated ?soft reset? on page 51 ? added note to table 15, ?hard reset signal timing,? on page 51 ? updated table 16, ?soft reset signal timing,? on page 52 ? added 2nd sentence in 2nd paragraph of ?standby modes? on page 53 ? added note to ?shutdown mode? on page 54 ? updated table 19, ?dc electrical definition s and characteristics?parallel mode,? on page 55 ? updated table 21, ?i/o timing specifications,? on page 58 ? updated table 22, ?two-wire serial bus characteristics,? on page 60 ? added note to figure 43: ?sequence of signals for otp memory operation,? on page 62 ? added note to figure 44: ?chief ray an gle (cra) vs. image height,? on page 64 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/1/08 ? in table 1, ?key performance parameters,? on page 1: ? updated cra from 25.03 to 25.11 max at 80% image height ? updated input clock frequency from 8-54 mhz to 10-48 mhz ? updated figure 1: ?typical configuratio n (connection),? on page 9, including notes. ? in table 3, ?signal descriptions,? on page 7: ? updated shutdown description ? updated extclk description ? added test_en ? in first paragraph of ?pll-generated clocks? on page 14, updated extclk input from ?8 through 54? to ?10 through 48? mhz. ? updated description in name column of r0x00003330, bit 8 in table 44, ?1: soc1 registers,? on page 174 ? in table 19, ?dc electrical definitions and characteristics?parallel mode,? on page 55: ?updated f extclk from 54 to 48 mhz ?changed v dd _mipi to v dd io_tx
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9p111: 1/4-inch 5 mp soc digital image sensor revision history mt9p111_ds rev. g pub. 5/15 en 67 ?semiconductor components industries, llc, 2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. ? fixed wrong symbol font in table 22, ?two-wire serial bus characteristics,? on page 60 ? fixed numbering sequence in various notes rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/11/2008 ?initial release

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